As is known to those skilled in the art, most metal-oxide-semiconductor field effect transistors (MOSFETs) are formed in a lateral orientation, with the current flowing parallel to the plane of the substrate or body surface in a channel between a source region and a drain region.
For an enhancement-mode n-channel MOSFET, the substrate is doped p-type and the source and drain regions are diffused or implanted with an n+ doping. A thin oxide layer separates the conductive gate from the silicon surface region between the source and drain regions. No current flows from the drain to the source region unless a conducting n-type channel is formed between the two n-type regions. When a positive voltage is applied to the gate relative to the substrate which is typically connected to the source, positive charges are in effect deposited on the gate metal and in response, negative charges are induced in the underlying silicon. These negative charges, that is mobile electrons, are formed within a thin inverted surface region of the silicon surface. These induced mobile electrons form the channel of the MOSFET and allow current to flow from the drain to the source. The effect of the gate voltage is to vary the conductance of the induced channel. Lowering the conductance lowers the barrier for the electrons to surmount between the source, channel and the drain. If the barrier is sufficiently reduced, by the application of a gate voltage in excess of a threshold voltage (VT) then there is a significant electron flow from the source to the drain. The threshold voltage is the minimum gate voltage required to induce the channel, i.e., form the inverted region to drive the MOSFET into a conducting state. For an n-channel device, the positive gate voltage must be larger than a positive threshold voltage before a conducting channel is induced. Similarly, in a p-type channel device (which is made on an n-type substrate with a p-type source and drain implants or diffusions) requires a gate voltage more negative than some threshold value to induce the required positive charge (comprising mobile holes) in the channel.
The threshold voltage is a function of several MOSFET physical and electrical parameters, including the oxide capacitance, the oxide thickness, the difference in work functions between the gate material (typically metal or polysilicon) and the silicon substrate, the channel doping and the impurity ion charge storage within the gate oxide. As will be discussed below, and according to the prior art, typically the substrate doping concentration is varied to form MOSFETs with differing threshold voltages on a single integrated circuit.
A plurality of planar n-channel MOSFET active devices fabricated on an integrated circuit chip are shown in the FIG. 1 cross-sectional view. A substrate 9 comprises a p+ region 50 and a p− layer 52, the latter typically grown by an epitaxial technique from the p+ region. MOSFETs 2, 4 and 6 are fabricated in the substrate 9. The MOSFET 2 is separated from the MOSFET 4 by a LOCOS (local oxidation on silicon substrate) region 10. Similarly, the MOSFET 6 is separated from the MOSFET 4 by a LOCOS region 12. Alternatively, the MOSFETS 2, 4 and 6 may be electrically isolated by shallow trench isolation (STI) techniques, wherein an anisotropic etch forms a trench in the region between two active devices. The is filled with an insulative material.
The MOSFET 2 comprises a gate 14, a source region 16 and a drain region 18 diffused in an n-type well 20. The MOSFET 4 comprises a gate 28, a source region 30 and a drain region 32 diffused in a p-type well 34. Finally, the MOSFET 6 comprises a gate 38, a source region 40 and a drain region 42 diffused in an n-type well 44. The gates 14, 28 and 38 are separated from the substrate 9 by a silicon dioxide layer 46, also referred to as a gate oxide layer.
As FIG. 1 is intended to be a simplified representation of a portion of an integrated circuit, the various contacts, interconnects, vias and metal layers are not shown and the features are not drawn to scale. It is particularly advantageous, especially in digital applications, to fabricate a combination of n-channel and a p-channel MOSFETs on adjacent regions of a chip. This complementary MOSFET (CMOS) configuration is illustrated in the form of a basic inverter circuit in FIG. 2, comprising a PMOSFET 60 and an NMOSFET 62. The drains of the MOSFETs 60 and 62 are connected together to form the output terminal (Vout). The input terminal (Vin) is formed by the common connection of the MOSFET gates. The operating voltage is designated by VD. In the FIG. 2 schematic, the PMOSFET 60 can be implemented by the structure of the MOSFET 2 in FIG. 1. The NMOSFET 62 can be implemented by the structure of the MOSFET 4 of FIG. 1.
State-of-the-art integrated circuit fabrication combines many different functions and subsystems onto a single chip, for example, combining different types of logic circuits, logic families and memory elements. For optimal performance and minimal power consumption individual devices on the integrated circuit may be operated at different operating voltages, i.e., the VD and VS values. Thus, the active devices must be fabricated with the necessary physical characteristics to accommodate the selected operating voltage. But in creating physical devices with these characteristics, it is also desirable to minimize and simplify the number of fabrication process steps.
For example, each of the MOSFETs 2, 4 and 6 of FIG. 1, may be designed to operate at a different operating voltage, i.e., VD/VS and/or at a different threshold voltage, VT. Generally, it is desirable to establish the device operating voltage at the minimum value that provides the required performance to minimize the power consumption of the devices, and thus overall, the power consumption of the chip. It is known, however, that there is a counter-effect; as the device operating voltage is reduced the operating speed of the device is also reduced. Therefore, to establish the optimum value for both of these parameters, it is necessary to operate the individual devices at operating voltages consistent with the required speed performance.
Given that there may be multiple operating voltages on a chip, there may also be multiple output voltages produced by the active elements and circuits of the chip. Thus the input circuit or device responsive to the preceding output voltage must be able to accommodate that output voltage and the active device must be designed to turn-on at the appropriate input voltage. For MOSFET and junction field-effect devices (JFETs) this turn-on voltage is the threshold voltage, the value of which is established by certain physical parameters of the device, as discussed above.
The prior art process of forming a plurality of MOSFETs with different threshold voltages is illustrated in FIGS. 3 through 6. At the conclusion of this process, each tub or well has a different doping density and therefore the MOSFET formed in each tub has a different threshold voltage. As shown in FIG. 3, a p+ substrate 100 carries an epitaxially grown p− layer 102 in which a plurality (three in this example) of n-type tubs are formed. Those skilled in the art recognize that the concepts presented are also applicable to the formation of p-type tubs or wells in a p or n-type substrate. To form the tubs, certain regions of the epitaxial layer 102 are masked by masks 104, 106, 108 and 110, with the space between these masks defining the tub regions. The arrows indicate the implantation of phosphorous or arsenic to create the n-type wells. Typically, the implant energy is 10 to 100 keV with a dose of 1E12 to 5E14 per cm2.
As shown in FIG. 4, this implantation step forms three n-type wells, 120, 122 and 124, each having the same doping density. If all other physical and electrical parameters for the three wells are equivalent, then the threshold voltages at this point in the process are also equivalent. FIG. 4 further illustrates the application of a second implantation to the well 120, while the wells 122 and 124 (and other areas of the substrate 100) are masked by masks 126 and 128. Thus the final doping density and the threshold voltage for the MOSFET formed in the well 120 are determined by the parameters of the FIG. 4 implant into the well 120.
Continuing with FIG. 5, the wells 120 and 124 are masked by masks 130 and 132, respectively. An additional implant step is executed for the well 122 to establish the final doping density and threshold voltage for the MOSFET formed therein. Finally, as shown in FIG. 6, the wells 120 and 122 are masked with a mask 134 and the remainder of the substrate 100 is masked, as necessary, by a mask 136. Now an additional implant is made in the well 124 for establishing its doping density and thus the threshold voltage for the MOSFET formed therein. Although this process is readily extendable to any number of MOSFETs on an integrated circuit, note that it requires a number of unique masks and masking steps based on the number of threshold voltages required on the integrated circuit. It is always desirable in the fabrication of integrated circuits to reduce the number of masks, as they are expensive to design and manufacture, and the number of fabrication process steps.
As is well known to those skilled in the art, at this point fabrication of the MOSFETs proceeds conventionally. For each MOSFET, a gate oxide is grown or deposited followed by formation of the gate. The gate serves as a mask for a first low-dose implant to form the lightly doped drain and source regions. A relatively thick layer of silicon dioxide is then deposited, for instance, by chemical vapor deposition and certain portions thereof are anisotropically etched, leaving only two sidewall spacers adjacent the gate. The spacers serve as a mask for a high-dose dopant implant to form the source and drain regions. After a drive-in diffusion step, the source and drain regions and the adjacent lightly-doped regions are formed.